Sampling clock offset estimation and correction in frequency domain for OFDM receivers

Abstract

Carrier frequency offset often occurs between wireless transmitter and receiver due to mismatch between the local oscillator in each of them. Standard-compliant communication systems define outer limits of tolerance of this mismatch expressed in parts per million (PPM). For high throughput systems like IEEE 802.11ac, this tolerance range is quite narrow. To meet such stringent specifications, number of techniques for correction of carrier frequency offset (CFO) are in practice, with varying degrees of complexity and compromise. Sampling clock is used for Analog-to-Digital conversion (ADC) operation in receivers and in Digital to Analog Conversion (DAC) in the transmitters which invariably are not synchronized. In this paper, a different method is proposed for correcting the sampling clock offset (SCO) in frequency domain with an assumption that same source is utilized for generating both carrier frequency for down-conversion and the sampling frequency used for (ADC) operation in the receivers. Depending upon the choice of modulation scheme, channel Signal-to-Noise ratio (SNR), Bit Error Rate (BER) and acceptable offset PPM, hardware designs suiting the requirement and compatible with algorithm adopted are suggested. This method has distinct advantages for different degrees of complexity of design vis-a-vis data rate.