Abstract
In order to exhaustively analyze the effects of fail- ures in safety-critical embedded systems, we have stud- ied safety analysis methods based on state transition di- agrams. However, the analytical worksheets and guide- words used in these methods are not suitable for analyz- ing parallel state transition diagrams, which represent the behavior of systems whose functions work in parallel. We propose a method whereby, if the severity of a deviation on a state transition diagram can be determined regardless of the other state transition diagrams, the total number of deviations to be analyzed can be reduced. Moreover, we show that techniques for containing the effects of devia- tions (e.g., memory protection) can limit their analytical area. Thus, we perform a Safety Analysis method based on a Parallel State Transition Diagram (SAPSTD). To clarify its effectiveness, we apply a conventional method and SAP- STD to the specifications of an example embedded system and compare the results of an evaluation.
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