S2DIO: an extended scalable 2D mesh network-on-chip routing reconfiguration for efficient bypass of link failures

Abstract

The paradigm of computing has shifted from computation-centric to communication-centric designs. Network-on-chip has emerged as an alternative interconnect mechanism for future multi-core designs. Transistor integration is approaching its limit, and this increases the susceptibility of the interconnects toward failures. Research efforts are directed toward improving the fault tolerance of these interconnects. Fault-tolerant routing such as segment-based and up*/down* are static by nature and require reconfiguration to circumvent failures. Failures may disrupt the connectivity of the network, and new routing instance needs to be configured in case old routing instance is unable to offer full connectivity. In this paper, we identify nodes affected by the failures and propose an extended scalable routing reconfiguration, called S2DIO. It performs reconfiguration of affected nodes by taking $$N^2$$ cycles for $$N \times N$$ mesh network, whereas state-of-the-art (ARIADNE) consumes $$N^4$$ cycles. Instead of routing tables, we employ logic-based routing and achieve significant improvements, i.e., $$30.7\%$$ in terms of area and $$29\%$$ in terms of power overhead for a $$16\times 16$$ mesh router. A novel algorithm for computation of new logic-based routing bits is also proposed in this paper. Our reconfiguration (S2DIO) improves average flit latency up to $$32\%$$ and throughput up to 19% for single-link failure in $$8\times 8$$ 2D mesh network-on-chip.