Abstract
A 56 bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39*7.39 mm/sup 2/, and it is mounted on a metallized ceramic substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 Model 60 (9375) engineering scientific accelerator card.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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