Runtime Bitstream Relocation based Intrinsic Evolvable System

Kaifeng Zhang,Shanzhu Xiao,Weidong Hu,Huanzhang Lu

doi:10.5755/j01.eee.20.6.4878

Kaifeng Zhang, Shanzhu Xiao + Show 2 more

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https://doi.org/10.5755/j01.eee.20.6.4878

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Abstract

Earlier evolvable hardware (EHW) platforms suffer from major drawbacks such as high area and delay overheads, high configuration memory overhead, low configuration speed and lack of flexibility. In this paper, we propose an intrinsic evolvable system on dynamic partial reconfigurable (DPR) platform using bitstream relocation technique to address these limitations. This relieves the overhead of configuration memory required to save the partial bistream (PB). In addition, the data transfer time between the configuration memory and the field programmable gate array (FPGA) is also reduced, which leads to a relatively high configuration speed. We implemented the proposed evolvable system using an FPGA board with an application of an adaptive finite impulse response (FIR) filter. The experimental result shows that the proposed system can achieve 116 × configuration speedup and 85 % configuration memory saving. DOI: http://dx.doi.org/10.5755/j01.eee.20.6.4878

Highlights

In the past decades, evolvable hardware (EHW) has received increasing attention from all over the world [1]–[6]
Overview of Intrinsic Evolvable System The intrinsic evolvable system we proposed is composed of the following modules: a PowerPC based embedded system, a custom internal configuration access port (ICAP) with the feature of bitstream decompression, and relocatable partitions
In the case of adaptive finite impulse response (FIR) filter, parameter adaptation refers to coefficient modification, and structural adaptation consists in topology modifications, for instance, the order or type of filters

Summary

Introduction

Evolvable hardware (EHW) has received increasing attention from all over the world [1]–[6]. In the intrinsic EHW approach, one of the most interesting features is that the calculation of fitness value of each candidate circuit, which is the most time consuming part in the whole evolutionary process, can be evaluated more quickly than in software simulation based extrinsic EHW [8]. Another visible advantage is that it can exploit physical properties of the electronic platform or environment and to provide some innovative features such as fault tolerance.

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