Abstract

The downscaling of electronic devices makes high field transport effects more important. In deep submicron technology high transversal and high lateral electric field exists. Application of drain voltage 1V results in electric field, which exceeds the silicon critical electric field. Electron temperature is then higher than lattice one and field dependent electron mobility must be considered. Due to small gate area we were able to activate one trap only and then in time domain two levels signal was observed. A systematic analysis of two level RTS signal was made to obtain information on capture and emission processes as a function of gate voltage, drain current and temperature for low and high lateral electric field. With increasing drain voltage capture time increases, while dependence on gate voltage is almost the same as for low drain voltage. For constant gate voltage and variable drain voltage emission process is independent on lateral field intensity, while capture time increases with lateral field ...

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