RTN and Annealing Related to Stress and Temperature in FIND RRAM Array

Chrong Jung Lin,Ya-Chin King,Chih Yuan Chen

doi:10.1186/s11671-018-2846-1

Abstract

In this work, an observation on random telegraph noise (RTN) signal in the read current of a FinFET dielectric RRAM (FIND RRAM) device is presented. The RTN signal of a FIND RRAM cell is found to change after the device being subjected to cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more frequent and intense RTN signals. The increase of noise levels in FIND RRAM cells can be alleviated generally by high temperature anneal, and with this concept, an on chip annealing scheme is proposed and demonstrated.

Highlights

We investigate the Random telegraph noise (RTN) noise in an n-channel FinFET-based FIND RRAM cell, which has already been successfully implemented in standard logic process in 1kbit arrays [12]
Through extensive measurement, it is found that RTN is more stable and observable in a FIND RRAM cell at its low resistance state (LRS)
In the study of cycling and annealing effect on RTN of FIND RRAM cells, the following section focuses on investigating cells at LRS

Summary

Introduction

Continuous scaling of CMOS technology improved the characteristics and performance of integrated circuits drastically in the past decade. As the technology node is scaled down below 20 nm, variations due to single atom/electron in device characteristics increases, for example, random dopant fluctuations (RDF), and bringing forth fundamental issues that cannot be overseen [1]. Random telegraph noise (RTN) is thought to be another major challenge for devices with small area, such as NAND Flash and RRAMs [5–11]. We investigate the RTN noise in an n-channel FinFET-based FIND RRAM cell, which has already been successfully implemented in standard logic process in 1kbit arrays [12]. Changes in the RTN in response to cycling stresses and high-temperature bake are observed. The effects of stress and temperature on the RTN noise in FIND RRAM cells is studied, and an on-chip annealing scheme is proposed to alleviate the after cycling time-variant read current noise

Background and Methods

Results and Discussion

Conclusion