RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage

Abstract

Functional test sequences play an important role in manufacturing test for targeting defects that are not detected by structural test. In practice, functional tests are often derived from existing design-verification test sequences and they suffer from low defect coverage. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a non-scan DFT technique at the register-transfer (RT) level that tackles the above problem in three steps. It can be used to increase the defect coverage for scan-based designs by making functional test sequences more effective in native (non-scan) mode. The proposed method selects a small set of control points, and through an efficient branch-and-bound strategy, determines an effective set of truth assignments to these control points (also called test modes). The original functional test is expanded by applying the same functional test sequence once with each selected test mode. Finally, a small set of state elements are chosen as observation points from the transitive fanout cone of the control points based on the number of recorded transitions. The proposed DFT method is evaluated in terms of the unmodeled defect coverage, and we introduce a new surrogate metric, called multi-segment long path sensitization, for the purpose of evaluation. Experimental results for the ITC'99 benchmark circuits, the Open RISC 1200 SoC benchmark, and the Scheduler module of the Illinois Verilog Model (IVM) show that the proposed non-scan DFT technique offers significant potential for ramping up the defect coverage of existing functional test sequences.