RTL power estimation in an HDL-based design flow

Abstract

Power estimation at the register-transfer level (RTL) is usually narrowed down to the problem of building accurate power models for the modules corresponding to RTL operators. It is shown that, when RTL power estimation is integrated into a realistic design flow based on an HDL description, other types of primitives need to be accurately modelled. In particular, a significant part of the RTL functionality is realised by sparse logic elements. The proposed estimation strategy replaces the low-effort synthesis that is typically used for this type of fine-grain primitives with an empirical power model based on parameters that can be extracted from either the internal representation of the design or from RTL simulation data. The model can be made scalable with respect to technology, and provides very good accuracy (13% on average, measured on a set of industrial benchmarks). Using a similar statistical paradigm, accurate (about 20% average error) models for the power consumption of internal wires are also presented.