RTL Delay Prediction Using Neural Networks

Abstract

Nowadays, the digital chip design flow starts with formal specifications, which are mapped to Register Transfer Level (RTL) models using different underlying implementation variants and (micro-) architectures. By doing so, a hardware designer predicts and resolves time-critical parts to achieve an RTL-design that intentionally meets all constraints after synthesis. However, wrong predictions can be detected only later in the design flow, thus leading to long design iterations. Classical methods estimating delay in early design stages are constrained to the type of components or are computationally expensive for larger designs. In this paper, we propose a Machine Learning-based approach to estimate pin-to-pin delays for RTL combinational circuits. To gain accuracy, we combine slew and delay estimation. To that end, a training set is built using features of components generated by a model-driven hardware generator framework. Ground truth labels for delays, slews, and their interdependencies are extracted using open-source tools for logic synthesis and static timing analysis. Evaluations in unseen designs show that the delay estimation has on average an accuracy of 87% and it is 13x faster compared with results of synthesis and timing analysis tools. Based on the estimation, critical areas of the design can be detected and proper microarchitecture decisions can be taken earlier in the design flow.