Abstract
We present a revised version of our previous RSFQ (Rapid Single Flux Quantum) microprocessor architecture and discuss approaches that we are using in the design of its functional units. In particular, the data processing pipeline built of D/sup 2/ cells, a 16-bit pipelined register block and an all-RSFQ self-reset decoder suitable for pipelined implementation are described in detail. Methods of VHDL description and verification of RSFQ circuitry are also discussed.
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