Abstract
This article presents the design of a Reed Solomon encoder circuit based on a concurrent LFCS -Linear Structure Concurrent Feedback-allowing the generation of code redundancy symbols in parallel, provided that you supply the k information symbols to encode simultaneously, the encoder provides at its output corresponding redundancy symbols. To achieve this development was generalized mathematical model describing the behavior of the encoder, the configuration was done in VHDL hardware description language of a Reed Solomon encoder, taking as case study the RS (7.3), the design was simulated validating the proposed operation, and finally the comparison of the encoder implementation between the sequential version and the version based on LFCS, obtaining a reduction of hardware components and optimizing the speed of response and power consumption. In conclusion, the proposed encoder design validates the concurrent model generalized from the correspondence with the architecture of LFCS.
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