RRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs

J.G Eldredge,B.L Hutchings

doi:10.1109/icnn.1994.374538

RRANN: a hardware implementation of the backpropagation algorithm using reconfigurable FPGAs

J.G Eldredge, B.L Hutchings

https://doi.org/10.1109/icnn.1994.374538

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Publication Date: Jun 27, 1994

Citations: 47

Affiliation: Brigham Young University

#Field Programmable Gate Arrays #Use Of Field Programmable Gate Arrays Resources + Show 8 more

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Abstract

Field programmable gate arrays (FPGAs) are an excellent technology for implementing neural networking hardware. This paper presents the run-time reconfiguration artificial neural network (RRANN). RRANN is a hardware implementation of the backpropagation algorithm that is extremely scalable and makes efficient use of FPGA resources. One key feature is RRANN's ability to exploit parallelism in all stages of the backpropagation algorithm including the stage where errors are propagated backward through the network. This architecture has been designed and implemented on Xilinx XC3090 FPGAs, and its performance has been measured. >

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