Routing design in optical networks-on-chip based on gray code for optical loss reduction

Abstract

An advanced electronics world and enhanced capability in nanoscale circuitry design require optimal integration in the design of electronic systems. Efforts are still being made to design and build integrated systems. In the old solutions, interconnections were established using the structure of buses. Bus-based solutions have lost their effectiveness against the demand for new technologies as a result of an increased number of circuits. Traffic was limited and, in some cases, even blocked by the buses. Systems-on-chip try to integrate processor, communication, and interface cores into one chip. One of the challenges facing this integration is routing between these cores. In networks-on-chip, bus-based structures have been replaced with networks very similar to computer networks. Communication is made between different parts by sending data packets through this network. Optical networks-on-chip include a new generation of chip-based networks, proposed as a new solution to the chip multiprocessor communications infrastructure, as well as a different solution to overcome the limitations of chip-based networks. Important features of these networks include increased communication bandwidth, reduced transmission latency, and reduced power consumption. They also face several challenges, such as routing for optical data transmission over optical layers. The current research proposes a routing algorithm based on mesh topology and gray code, which uses a packet switching method and a random traffic pattern to improve routing. The newly proposed method can select the different source and destination nodes by choosing the path with the lowest optical loss. A comparison between the result of the reduction in the optical loss in the proposed routing algorithm and that of the dimensional sequential algorithm shows a 40 % improvement in the proposed method.