Room-temperature and high-quality HfO2/SiO2 gate stacked film grown by neutral beam enhanced atomic layer deposition

Beibei Ge,Seiji Samukawa,Yiming Li,Kazuhiko Endo,Yi-Ho Chen,Jenn-Hwan Tarng,Takuya Ozaki,Daisuke Ohori

doi:10.1116/6.0001607

Abstract

This study reports the fabrication of the high-quality hafnium dioxide (HfO2) film at room temperature (20–30 °C) using the neutral beam enhanced atomic layer deposition (NBEALD) we developed. The HfO2 film was fabricated using tetrakis(ethylmethylamino)hafnium (TEMAH) as the Hf precursor and O2 NB as the oxidant. Argon gas was used for the carrier and purge gases. The HfO2 film-deposition process consists of 5-s TEMAH feed, 5-s Ar purge, 5-s O2 gas injection, 20-s O2 neutral beam irradiation, and 5-s Ar purge. The HfO2 film exhibited a saturated growth per cycle of 0.18 nm/cycle and a high-quality film with low C contamination (2.7%), N contamination (3.9%), and a good O/Hf ratio (2.0) was achieved. The film also had an ideal refractive index of 1.9. Additionally, continuously grown high-quality HfO2 and silicon dioxide (SiO2) gate oxide films (stacked HfO2/SiO2 gate oxide film) were successfully fabricated at room temperature. This film has the potential to decrease the thermal budget, thus enabling high flexibility when designing semiconductor structures. These findings demonstrate the effectiveness of our NBEALD in forming high-k gate stack structures.

Highlights

The transistor technical node has been scaled down to 5 nm, and 3-nm transistors will be put into manufacturing beginning 2022.1 The main components of the latest integrated circuits (ICs) are metal-oxide-semiconductor field-effect transistors (MOSFETs).The physical thickness of the conventional gate dielectric material, i.e., silicon dioxide (SiO2), has become thinner
This study reports the fabrication of the high-quality hafnium dioxide (HfO2) film at room temperature (20–30 °C) using the neutral beam enhanced atomic layer deposition (NBEALD) we developed
The thickness increased as the number of cycles increased, and growth per cycle (GPC) was 0.18 nm/cycle, which is in good agreement with the monoclinic HfZO bond length avs.scitation.org/journal/jva

Summary

INTRODUCTION

The transistor technical node has been scaled down to 5 nm, and 3-nm transistors will be put into manufacturing beginning 2022.1 The main components of the latest integrated circuits (ICs) are metal-oxide-semiconductor field-effect transistors (MOSFETs). Hafnium dioxide (HfO2) film, as a high-k material (high dielectric constant: 20–25), has a conduction band shift greater than 1 eV to Si, which can effectively suppress the generation of tunneling currents when the gate dielectric layer is thinned It has good thermodynamic stability and good lattice-matching properties when in contact with Si, making it the most promising new material to replace the conventional complementary-MOS (CMOS) gate insulating layer material, i.e., SiO2.4–6 The CMOS gate layer is typically formed using film-deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

EXPERIMENT

RESULTS AND DISCUSSION

SUMMARY AND CONCLUSIONS