Role of film intrinsic stress in packaging of multi-layer microelectronic structures

Abstract

Internal stress due to material CTE and Young's modulus mismatch in microelectronic and micro-electromechanical system (MEMS) structures is critical to their reliability. It is well understood and hence its impact is generally controllable. However, the film intrinsic stress develops as a function of processing. The level of stress and how it changes with additional processing or environmental exposure is still not well understood. This stress is typically neglected in response prediction as its magnitude, behavior and response impact are not well known. Intrinsic film stress can play a substantial role in enhancing or degrading the response of multi-layer structures. Intrinsic stress can cause failures or can mitigate catastrophic failures. Thin film intrinsic stress is processing-related so, it may be controlled by modifying processing parameters. In addition, these stresses are also dependent on film size and thickness. These requirements point to a need for a measurement and a response prediction capability. The measurement capability should be capable of addressing the typical size and thickness seen in actual devices and MEMS structures. In this paper, an approach for measuring intrinsic film stresses in small features on microelectronic and MEMS devices, using a hybrid experimental-cum-numerical approach is authored. Two microelectronic applications are given to highlight the importance of intrinsic stress on device performance.