Role of annealing temperature in the oxide charge distribution in high- $$\kappa $$ κ -based MOS devices: simulation and experiment

Abstract

The effect of rapid thermal annealing on the oxide charge distribution of Al/HfO$$_2$$2/SiO$$_2$$2/Si metal---oxide---semiconductor structures are studied using technology computer-aided design (TCAD) simulations and experiments. The simulated electrical characteristics are compared with experimentally obtained data. The interface traps are found to be nonuniform in nature and laterally distributed following a Gaussian profile. The distribution of interface trap charges arises because of spatial electric field variation in the oxide film upon gate bias application. The interface trap density is found to decrease with increase in annealing temperature. It is further observed that, at higher annealing temperature, the fixed oxide charge density increases due to interfacial Hf silicate formation.