Role of an encapsulating layer for reducing resistance drift in phase change random access memory

Bo Jin,Dong-Hai Pi,Hyoung Seop Kim,Jungsik Kim,M Meyyappan,Jeong-Soo Lee

doi:10.1063/1.4905451

Bo Jin, Dong-Hai Pi + Show 4 more

Open Access

https://doi.org/10.1063/1.4905451

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Abstract

Phase change random access memory (PCRAM) devices exhibit a steady increase in resistance in the amorphous phase upon aging and this resistance drift phenomenon directly affects the device reliability. A stress relaxation model is used here to study the effect of a device encapsulating layer material in addressing the resistance drift phenomenon in PCRAM. The resistance drift can be increased or decreased depending on the biaxial moduli of the phase change material (YPCM) and the encapsulating layer material (YELM) according to the stress relationship between them in the drift regime. The proposed model suggests that the resistance drift can be effectively reduced by selecting a proper material as an encapsulating layer. Moreover, our model explains that reducing the size of the phase change material (PCM) while fully reset and reducing the amorphous/crystalline ratio in PCM help to improve the resistance drift, and thus opens an avenue for highly reliable multilevel PCRAM applications.

Highlights

Chalcogenide-based phase change random access memory (PCRAM), repeatedly switching between crystalline and amorphous phases[1] has attracted significant interest as one of the viable contenders for the generation nonvolatile memory due to its faster write/read speed, non-volatility, and longer endurance
Phase change random access memory (PCRAM) devices exhibit a steady increase in resistance in the amorphous phase upon aging and this resistance drift phenomenon directly affects the device reliability
A stress relaxation model is used here to study the effect of a device encapsulating layer material in addressing the resistance drift phenomenon in PCRAM

Summary

INTRODUCTION

Chalcogenide-based phase change random access memory (PCRAM), repeatedly switching between crystalline (low resistance) and amorphous (high resistance) phases[1] has attracted significant interest as one of the viable contenders for the generation nonvolatile memory due to its faster write/read speed, non-volatility, and longer endurance. Numerous studies have focused on device performance of various materials (GeTe,[2,3] In2Se3,4–6 GeSb7 and GeSbTe alloys8,9) in the nanowire (NW) form due to the potential for scaling with reduced device footprint and reduced inter-cell thermal interference Issues such as resistance drift phenomenon[10] and material scaling problems[3,5,9] have been raised through the course of PCRAM development in the last decade. In the subsequent drift regime, the residual stress (σ1) is continuously released over a relatively long time.[10] In order to reduce the resistance drift, an effective method to increase the stress relaxation is needed during the amorphization process since the drift coefficient is directly related to the residual stress.[15].

MODEL AND SIMULATION

Fully reset

Partially reset

CONCLUSION