Robustness and performance analysis on high speed ASIC design with canonical statistical timing model

Abstract

This paper discusses the robustness and performance on H tree structure with canonical statistical timing model. We compare the deterministic skew and statistical skew to analyze the design health. With the sensitivity distribution available at the end of statistical timing, we make the robustness diagnostic to reveal key variation sources and optimization scheme. The skews under intra-chip variation are also evaluated to select best H tree structure.