Robust Through-Fin Avalanche in Vertical GaN Fin-JFET With Soft Failure Mode

Abstract

We study the inherent ruggedness of the avalanche through the fin channel, a new avalanche mode in a vertical GaN power Fin-JFET, through single-pulse and repetitive avalanche circuit tests. By turning on the gate during avalanche, the major avalanche current path migrates from the p-GaN gate to the n-GaN fin channel. The single-pulse critical avalanche energy density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> ) was measured to be 10 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is the highest reported in GaN transistors. The Fin-JFET withstood over 3700 repetitive avalanche pulses at 70% of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {AVA}}$ </tex-math></inline-formula> . It exhibits a failure-to-open-circuit signature in single and repetitive avalanche. This soft failure mode allows the device to retain its full breakdown voltage, which is highly desirable for system robustness. By contrast, the through-gate avalanche in Fin-JFETs and the reported avalanche in Si and SiC transistors all show a destructive, failure-to-short-circuit signature. These results show the viability of soft avalanche failure in power devices, provide key robustness references for GaN devices, and suggest the fundamental superiority of moving the avalanche path away from the major blocking junction.