Abstract
Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failures is presented. As compared to previous methods, the main advantage of this is the ability to tolerate non-ideal conditions, for example, under the presence of certain core logic faults or for those faults that manifest themselves intermittently. The diagnosis problem is first formulated as a ‘delay insertion process’. Upon this formulation, two algorithms – a ‘greedy’ algorithm and a so-called ‘best-alignment-based’ algorithm – is proposed. Experimental results on a number of practical designs and ISCAS'89 benchmark circuits are presented to demonstrate its effectiveness.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
