Abstract
This paper addresses the efficient implementation of a robust gradient-based optical flow model in a low-power platform based on a multi-core digital signal processor (DSP). The aim of this work was to carry out a feasibility study on the use of these devices in autonomous systems such as robot navigation, biomedical assistance, or tracking, with not only power restrictions but also real-time requirements. We consider the C6678 DSP from Texas Instruments (Dallas, TX, USA) as the target platform of our implementation. The interest of this research is particularly relevant in optical flow scope because this system can be considered as an alternative solution for mid-range video resolutions when a combination of in-processor parallelism with optimizations such as efficient memory-hierarchy exploitation and multi-processor parallelization are applied.
Highlights
Motion estimation has been deeply investigated during the last 50 years; it is still considered by the scientific community as an emerging field of special interest due to the plethora of applications that supports the interpretation of the real world, such as navigation, sports tracking, surveillance, video compression, robotics, vehicular technology, etc
There are only few approaches existing in the literature exploiting gradient-based motion estimation methods in digital signal processor (DSP) platforms as the one proposed by Shirai et al [16] in early 1990s, implementing the classical method of Horn-Schunck algorithm [17] using many boards with a TMS320C40 DSP each
We provide a list of incremental optimizations applied in order to improve the performance of our implementation on the multi-core DSP
Summary
Motion estimation has been deeply investigated during the last 50 years; it is still considered by the scientific community as an emerging field of special interest due to the plethora of applications that supports the interpretation of the real world, such as navigation, sports tracking, surveillance, video compression, robotics, vehicular technology, etc. There are countless proposals under lowpower conditions for pattern-matching family algorithms, but most are in the video compression field [11,12] Another approach with central processing units (CPUs) [13] presents a parallel scheme applied to a model based on well-known Lucas-Kanade approach, which reduces power consumption in terms of thermal design power (TDP) and still meets the real-time requirements when low-power chipsets (TDPs of 20 to 30 W) are used. There are only few approaches existing in the literature exploiting gradient-based motion estimation methods in DSP platforms as the one proposed by Shirai et al [16] in early 1990s, implementing the classical method of Horn-Schunck algorithm [17] using many boards with a TMS320C40 DSP each This algorithm supplements optical flow constraint with regularizing smooth terms, while our work uses spatio-temporal constancy. The amount of data produced at this stage is quantified close to ((N −L)×nx×ny×nTemp filters×nSpat filters×nθs)
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