Abstract

One of the main obstacles for memristors to become commonly used in electrical engineering and in the field of artificial intelligence is the unreliability of physical implementations. A non-uniform range of resistance, low mass-production yield and high fault probability during operation are disadvantages of the current memristor technologies. In this article, the authors offer a solution for these problems with a circuit design, which consists of many memristors with a high operational variance that can form a more robust single memristor. The proposition is confirmed by physical device measurements, by gaining similar results as in previous simulations. These results can lead to more stable devices, which are a necessity for neuromorphic computation, artificial intelligence and neural network applications.

Highlights

  • Since the theoretical [1] and practical [2] discovery of memristors, they have been extensively studied [3,4,5] as elementary building blocks for artificial intelligence and neuromorphic computing applications

  • Research has been done [6] to find optimal materials that satisfy these expectations, but even there are other possibilities to further increase the capabilities of memristors

  • The measured memristor devices are made of Ge2 Se3 and Ag based chalcogenide dielectric with W (Tungsten) conductors

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Summary

Introduction

Since the theoretical [1] and practical [2] discovery of memristors, they have been extensively studied [3,4,5] as elementary building blocks for artificial intelligence and neuromorphic computing applications. The expected properties of memristors for such applications are wide and analog resistance range, low variance of device parameters and high device stability during long-term operation. Research has been done [6] to find optimal materials that satisfy these expectations, but even there are other possibilities to further increase the capabilities of memristors. The first one is having two clearly distinguishable states and these state declarations should apply to every element in a memory array. To reach the performance of the current complementary metal–oxide–semiconductor (CMOS) technology’s

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