Robust Estimation of FPGA Resources and Performance from CNN Models

Abstract

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly popular for implementing convolutional neural networks (CNNs) due to their low latency and very high energy efficiency. However, most FPGAs are resource-scarce and efficient mapping of CNN can quickly become a challenging task. The requirement of FPGA resources, latency, and power is affected by many parameters, including the CNN architecture and the level of computational parallelism. In practice, a software designer first explores various CNN architectures in software to improve architecture’s validation accuracy. Once an architecture is finalized, the designer ports the architecture design to FPGA for inference acceleration. The mapping process undergoes performance optimization by tweaking many design-related parameters during the design space exploration and changing the operating frequencies. The entire process is highly time-consuming. In this paper, we have presented a machine learning-based two-stage estimator for assisting in designing an FPGA-based CNN accelerator. Our Global Predictor assists in making accurate estimates of FPGA resource requirements and design latency from CNN architecture and hyperparameters expressed in Python. This assists in choosing a subset of high validation accuracy and feasible designs for mapping on FPGA. Our Detailed Predictor assists in making accurate estimates of FPGA post-route resource requirements, design latency, and final clock period for the chosen subset of designs after applying high-level synthesis level (pragma and frequency) optimizations. Our proposed estimation methodology enables a software engineer to obtain rapid and accurate estimates of the final implementation Quality of Results without executing FPGA design flows. We trained and tested our model for Xilinx Zynq Ultrascale + and Kintex-7 devices. We achieved an average prediction error of less than 9% and 4% for stages one and two, respectively.