Robust circuit optimization under PVT variations via weight optimization problem reformulation

Abstract

Robust design in analog integrated circuits (ICs) is intricate due to process variations, culminating in notable performance uncertainties. Contemporary surrogate-based techniques depend on lengthy pre-training and are prone to prediction inaccuracies amidst process, voltage, and temperature (PVT) fluctuations. This paper introduces a framework that amalgamates a problem reformulation strategy with an evolutionary algorithm, expediting robust analog IC design in the face of PVT variations. Initially, by segmenting decision variables into subgroups and correlating them with weight variables, the decision space is adeptly reconstructed. An indicator function is subsequently utilized to minimize the objective space’s dimensionality, thereby reshaping the original problem into a low-dimensional single-objective optimization problem. Given the reduced dimensionality of both objective and decision spaces, the Bayesian optimization algorithm is invoked to efficiently diminish performance disparity under variations. Consequently, a collection of quasi-optimal, robust solutions is acquired. In the final phase, a multi-objective evolutionary algorithm ensures the even distribution of these quasi-optimal solutions along the approximate Pareto optimal front. To validate the effectiveness of our framework, we conducted tests on three integrated voltage references and compared the results with four cutting-edge methods. The empirical data highlight the superior performance of our framework, which yields a 3 to 40-fold increase in the quality factor and a 30% to 60% reduction in necessary function evaluations. Additionally, the framework led to a 40% to 70% decrease in the overall execution time.