Abstract
This paper addresses the functional robustness and fault-tolerance capability of very-deep submicron CMOS and single-electron transistor (SET) circuits. A set of guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. Empirical results based on SPICE simulations show that the proposed design method improves fault immunity at transistor level. Graceful degradation of circuit performance allows recovery of information, where classical circuits would fail.
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