Abstract
Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.
Highlights
Low power consumption is nowadays paramount for digital integrated circuits
A major consequence at circuit level is on the minimum-energy level Emin which stopped scaling from 90 nm node and increases significantly at 45 nm node because of the combined effects of subthreshold swing, drain-induced barrier lowering (DIBL), gate leakage and statistical variability [29]
We focus in this paper on techniques to reliably operate ULV logic at the minimum-energy point in 65/45 nm CMOS technologies
Summary
Low power consumption is nowadays paramount for digital integrated circuits. High-performance chips such as multi-core processors for servers are power constrained by the die temperature limit and by both the cooling and electricity costs [1]. Esw is effectively reduced thanks to lower on-chip capacitances CL while gate delay at ultra-low voltage is improved thanks to a higher subthreshold Ion current resulting from the scaled Vt [12] This leads to boosted speed performances at the minimum-energy point. A major consequence at circuit level is on the minimum-energy level Emin which stopped scaling from 90 nm node and increases significantly at 45 nm node because of the combined effects of subthreshold swing, DIBL, gate leakage and statistical variability [29] This Emin increase can be limited by choosing the optimum MOSFET (medium gate length and low Vt ) within a versatile yet standard CMOS technology menu with good speed performances and negligible area penalty [23]. We review the constraints on minimum Vdd to ensure circuit robustness given this high local variability in nanometer CMOS technologies
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