Abstract
This paper presents a reconfigurable matrix based built-in self-test processor (RMBITP) which makes use of both software commands and reconfiguration of the design under test (DUT). The RMBITP self-test algorithm is based on a new 3-dimensional (stages) output data compaction scheme for minimizing the probability of aliasing error, the BIST time, and the engineering development effort while limiting the percentage BIST overhead to 15% or less. To illustrate the concept, the built-in selftesting of large complex designs ranging from 1 to 5 million gates is presented.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
