RISC-V Processors for Spaceflight Embedded Platforms

Abstract

Reduced Instruction Set Computer Five (RISC-V) is an open-source processor instruction set architecture which is rapidly gaining popularity in space applications. Not only can this architecture be implemented in standalone application specific integrated circuit (ASIC) hardware processors, but can be configured within field-programmable gate array (FPGA) fabrics. This paper will discuss the benefits and challenges of using RISC-V soft-cores within radiation-tolerant FPGAs for embedded space applications. Spacecraft are limited by size, weight, power, and cost (SWAP-C), and most rely on both FPGAs and discrete microprocessors to meet onboard processing needs. With advances in capacity for radiation-hardened FPGAs, it is now feasible to implement an advanced soft-core microprocessor (or even multiple cores) within the FPGA itself. This has potential to reduce part count and simplify designs greatly, make efficient use of spare FPGA capacity, and reduce the overall SWAP-C of spaceflight computers. The research team tested the latest RISC-V FPGA offerings from Microchip (product name Mi-V) and CAES (product name NOEL-V). The performance of these processor implementations was measured on a standard benchmark suite across multiple operating systems on evaluation hardware. This paper describes our test methodology, analysis, and conclusions.