Ring based Optical Network-on-Chip

Abstract

With the increasing number of IP cores that are integrated into a system-on-chip (SoC), the interconnection between different cores has become crucial to achieve high performance. Optical Network-on-Chip (ONoC) has emerged as a high efficiency interconnection for the future generation of many-core SoCs. ONoC can achieve high bandwidth, low delay, low interference, and low power consumption, which makes it promising in future SoC design. In this paper, a new optical interconnection is proposed to interconnect the IP cores and caches in a chip. It is constructed by levels of rings. All the IP cores and corresponding caches are arranged in the rings respectively. The floorplan is carefully designed with consideration about reducing waveguide crossings. A new optical router is proposed and its insertion losses are analyzed. Finally, a simulator based on OPNET is carried out to evaluate the network performance in terms of End-to-End delay and throughput. The simulation results demonstrate that the proposed architecture can implement well and achieve good performance.