Rigorous statistical process variation analysis for quarter-μm CMOS with advanced TCAD metrology

Abstract

Effects of statistical process variation on 0.35 /spl mu/m CMOS performance have been rigorously characterized using a new calibrated TCAD metrology. To achieve the variation analysis, a series of TCAD was conducted based on DoE with optimum variable transformations, which results in an RSF (Response Surface Function) for threshold voltage (Vth) and saturation drain current (Ids). A new global calibration of the RSF based on experimental data gives excellent accuracy of the RSF model within 0.02 V error in the Vth and 3% error in the Ids. Using the calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of gate-oxide formation process (oxide thickness: Tox) shows the most significant effect on the NMOS /spl delta/Ids in the production process. Furthermore, we have designed an optimized 0.25 /spl mu/m CMOS process and device based on the RSF, and also predicted its process variation effect on the device performances. It is clarified that the Vth and Ids variations of the 0.25 /spl mu/m CMOS show less than 10% for Ids in production level process, which is a similar value to the 0.35 /spl mu/m CMOS experimental data. Also additional TCAD for MOS model parameter generation, for the 0.25 /spl mu/m device, was conducted to allow circuit-designers to use predictive worst-case circuit design parameters before experimental chip fabrications.