RF Performance of Stacked Si Nanosheets/Nanowires

Abstract

RF performance of stacked Si nanosheet/ nanowire nFETs considering 6/10-lateral-stack 4-finger transistor array is studied and optimized by validated TCAD simulation. Compared with nFinFETs, stacked Si nanosheets/nanowires can have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.0/ 2.2\times $ </tex-math></inline-formula> cut-off frequency (435/480 vs 215 GHz) and 1.6/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.3\times $ </tex-math></inline-formula> maximum oscillation frequency (405/575 vs 251 GHz) with an optimized equivalent oxide thickness of 0.8nm, a gate length of 18nm, and a floor number of 4/6, using the double-sided gate contact array layout. Because of the small channel cross section of nanowires and the lower carrier density at central nanosheets than edges, stacked nanowires can achieve better RF performance than stacked nanosheets. As the lateral stack number increases to enhance the output power, the contact over active-gate layout can maintain both the high cut-off frequency and the high maximum oscillation frequency of stacked nanosheets and stacked nanowires.