RF Performance Evaluation of Nanoscale FDSOI MOS transistors

Narendra Yadava,R K Chauhan

doi:10.17485/ijst/2019/v12i40/148011

Narendra Yadava, R K Chauhan

Open Access

https://doi.org/10.17485/ijst/2019/v12i40/148011

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Abstract

Objectives: In this work, the performance of single-gate and double-gate FD-SOI MOSFETs has been investigated in order to find out its utility RF applications. Methods/statistical analysis: The small-signal equivalent model is utilized to obtain the Y parameter of the devices and from which the minimum noise Figure and S parameter of the devices are derived and provides its applicability in the design of RFICs. The analysis is carried out using the Silvaco 2D ATLAS tool. Findings: The simplified small-signal equivalent models for both the devices are developed to analyze its high-frequency response more accurately, and to extract other important high-frequency (RF) parameters. Application/improvements: The derived S parameters are used to evaluate its high-frequency (RF) losses. In the SG FD-SOI MOSFET, the Insertion loss is 2.47 dB, the Transmission loss is 2.48 dB and the Reflection loss is 1.02 dB lower in comparison to DG FD-SOI MOSFET while its Return loss is 0.05 dB higher in comparison to that of DG FD-SOI MOSFET.Keywords: FD-SOI MOSFET, RFICs, Leakage Current, Power Dissipation, RF Frequency

Highlights

The demand for high-performance wireless and RFIC applications with low power consumption is increasing day by day
For all the figures shown here, the line with square mark denotes the behaviour of SG FD-SOI MOSFET and the line having circular mark denotes the behaviour of DG FD-SOI MOSFET
The leakage current in DG FD-SOI MOSFET is found to be 0.15 A/μm while it is equal to 0.09 A/μm in the single gate FD-SOI MOSFET

Summary

Introduction

The demand for high-performance wireless and RFIC applications with low power consumption is increasing day by day. The challenges arise due to the adverse effect imposed by the small geometry devices (SCEs).[3,4,5,6]. To overcome the forestated hindrances, since last two decade researchers are making great effort and even various device designs already have been proposed.[7,8,9,10,11,12,13] SOI technology out of several MOS technology is preferred due to its several advantageous features like it highly suppress the leakage currents by using a buried oxide (BOX) insulating layer underneath the channel region and its fabrication is easy and cost-efficient.[14,15,16,17]

Objectives

Results

Conclusion