RF Modeling of Through Silicon Vias (TSVs) in 3D IC

Abstract

As the size of transistor keeps shrinking, advance of CMOS technology becomes more difficult and will eventually reach the physical limitation. To continuously reduce the form factor of the system with multiple chips, one straight forward solution is using stacked dies, called three-dimensional integrated circuits (3D IC). Recently, the technology of Through Silicon Vias (TSVs), developed mainly for realizing 3D IC, attracts much attention. For the design of 3D IC using TSV, the electrical characteristics and the associated SPICE model of TSVs play extremely important roles. The studies of TSV test structures and RF modeling have been reported [1]-[2]. Differing from the conventional planar IC, it is rather difficult to avoid the undesired parasitics in direct on-wafer measurement for the 3D test structure. Therefore, accurate RF modeling of the TSV, involving the test structure design and parameter extraction, is still an issue and need to be studied further. In this paper, we propose an effective approach for designing the TSV test structures and extracting the equivalent circuit model parameters. The one-port test structures, consuming only a small chip area, are employed to solve the difficulty encountered in the typically used two-port methods. The proposed equivalent model, which composed of R, L, C, and G, is based on the physical structure of the TSV and is verified up to 50 GHz. The parameters calculated using the analytical equations confirmed that the proposed approach leads to a well-defined physical-based model.