Abstract
The Cavity Simulator was designed to simulate RF signals coming from the superconducting accelerating module in response to the signals generated by the LLRF control system. Design of this device is a part of Polish Electronics Group in-kind contribution to the European Spallation Source project. PEG will assemble, install and test all LLRF control systems for superconducting elliptical cavities used in medium and high beta sections of the ESS linac. To avoid the risk of damaging real cavities, each system will be first tested with the Cavity Simulator. The cavity model is implemented in a high speed FPGA and the device operates at 704.42 MHz. A dedicated front-end is needed to interface between the digital circuits and RF signals. Its main function will be digitizing the signal coming from the LLRF control system and generating the response calculated in the FPGA. For this purpose down-converter and vector modulator circuits with a set of data converters are used. This circuits require additional signals like clock and LO, which are also generated by the RF circuitry. In this paper the design of the Cavity Simulator RF front-end is presented.
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