RF and linearity distortion performance estimation of dopingless symmetric tunnel FET (DLSTFET)

Abstract

ABSTRACT This work eradicates the issue of area penalty in logic designing due to unidirectional flow of current in conventional TFET. The dopingless symmetric tunnel FET (DL-STFET) device structure also has immunity towards random dopant fluctuations (RDFs) and trap-assisted tunnelling along with easy fabrication and a lower thermal budget. The device structure has a better drive current and subthreshold swing (SS). Furthermore, the sensitivity of the device with respect to the device dimension variation such as channel/gate length, body thickness and silicon pad thickness has also been studied on device dc, analog/RF and linearity parameters. The device dc parameters are immune towards the device dimensional variations, whereas the analog/RF and linearity parameters are sensitive to device dimension variation. The analog/RF parameters such as , , , , GBW, TGF and TFP have been studied. Furthermore, the linearity parameters such as , , , , and have also been analyzed here. This study provides the direction for designing DL-STFET for better analog/RF performance with least linearity distortions.