Rework techniques process evaluation for chip scale packages

Abstract

The packaging formats, chip scale package (CSP) and ball grid array (BGA) have allowed significant reductions in component size compared to conventional surface mount devices (SMD) such as quad flat packs (QFP). However, the position of the solder joints formed (underneath the chip) after reflow means that visual inspection is impossible. For the defective chip, the only realistic method of rework is to remove and replace it. Component removal can be easily achieved, however replacement may be more complex. Difficulties in the procedure may arise from loss of terminations during the removal process, and high component population densities on printed circuit boards (PCB) may also inhibit access to the component pad site. The typical rework process consists of a number of steps including; component removal, PCB pad clean-up, flux or solder paste application, component placement and reflow. In this paper, we evaluate the pad clean up stage of the CSP rework process, including the design and analysis of a variety of solder paste or flux deposition techniques. Two PCB pad-cleaning methods have been compared and conclusions drawn from the resultant pad finish. Four deposition techniques have been assessed; these include mini-stencil, dip transfer, on- and off-contact stamping. Mini-stencil is the traditional method used in the electronics manufacturing industry for the deposition of solder paste onto reworked component sites. The remaining deposition techniques have been developed in order to overcome access restrictions that might exist on densely populated PCB's.