Abstract
As the semiconductor technology enters into sub14nm regime, very-large-scale-integration (VLSI) circuits are featured with increasing integration density and growing power consumption, thereby jeopardizing the robustness of a power delivery (PD) system. While decoupling capacitance (decap) insertion remains as the most effective method to mitigate transient noise of a PD system, too much decap insertion not only incurs additional cost but also adds up unnecessary leakage. It is highly desired to have an efficient optimization method for decoupling allocation. This paper revisits the conventional extended adaptive voltage positioning (EAVP) method but proposes new modeling and optimization schemes to overcome the impracticality and in-efficiency of EAVP. The modified EAVP can be integrated into a practical PD design flow and achieve 33.5% decoupling resource saving or 16.8% noise reduction.
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