Abstract
most of the operations performed by any complex system need a multiplier. Hence, multiplier based on FFT is the desired aim. In this paper, we have presented a review of parallel polynomial multiplier based on FFT using Indian Vedic mathematics. Parallel polynomial multipliers were optimized for throughput and area resources, respectively. These multipliers are used for multiplication of different polynomial numbers based on exponential type, power type, etc. FFT system is used for multiplication so complex multiplier is the main part of this design. The coding of the design can be done in VHDL. For synthesis and simulation of the design Xilinx ISE EDA tool can be used.
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