Abstract
In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools.
Highlights
A charge pump is designed based on capacitors and NMOS, PMOS switches it is one of the converters such as dc-dc converters, here the purpose of the capacitor acts as a storage media it will produces higher outcomes.charge pump is act as a switching element and it will control the connection of voltage flow to the capacitor
Charge pump is a switching device based on capacitor it operated by low supply voltage but need high voltage to drive step-up transformer
If clock phase was properly applied for this charge pump can allow the charge only one direction in forward position when the MOS switches turned ON and OFF .in this charge pump specially constructed at each stage by dynamic inverters it will be control the ON/OFF operation at each stage
Summary
A charge pump is designed based on capacitors and NMOS, PMOS switches it is one of the converters such as dc-dc converters, here the purpose of the capacitor acts as a storage media it will produces higher outcomes (output power is high compared input power).charge pump is act as a switching element and it will control the connection of voltage flow to the capacitor. In VLSI technology is a day’s very popular and it has more advantages such as low power, low area, low time based on fabrication process, it will always depends on CMOS technologies These technologies is decreased the power dissipation but it cannot able reduce the leakage current and the circuit delay. In this circuit need to reduce the delay at that same time decreased the leakage/static power or current by using VLSI methodology, that name is called low threshold .in this circuit applying low threshold achieving by power gating method In this power gating technique has many methods to reduce the leakage such as sleep mode, active, mode, dream mode, MTCMOS mode, here using MTCMOS
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