Abstract
Finite State Machines (FSM) are an important category of digital circuits. Simply put, an FSM starts from a certain state, receives a sequence of inputs, changes its internal states, and produces a sequence of outputs. We define the reverse of a given FSM as an FSM that given the original final state and the reversed sequence of original outputs, can produce the reversed sequence of original inputs. Implementing such an FSM has uses in testing, fault tolerance and debugging digital circuits including processors. We present techniques that can produce a deterministic reverse FSM from a given deterministic FSM. The overhead is at most one extra state, plus ? log 2 (NP) ? extra output bits in case in the original FSM at most N states share the same next state and output value.
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