Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic

Abstract

In this work, Energy efficient Binary content addressable memory (BiCAM) is designed using reversible logic which is in high demand in fields of quantum computing, nano technology, data centric computing, software-defined networks and wide variety of high speed applications. BiCAM performs search operation in a single clock cycle. Binary content addressable memory (BiCAM) design based on reversible logic reduces power dissipation. Due to minimum heat dissipation, Reversible logic has gained its interest in recent years. A novel design of BiCAM array using reversible logic gates with transmission gate logic improves speed and reversibility ensures low power. The proposed reversible logic based 4x3 BiCAM array using transmission gates is implemented using mentor graphics at 130nm technology with Vdd=1.2V shows 95.2% efficiency in power compared to CMOS based BiCAM design. All reversible logic gates used in BiCAM design as analysed using transmission gate logic and compared with conventional gates.