Reversible circuit design for GCD computation in cryptography algorithms

Abstract

SummaryThe implementation of cryptography algorithms is constantly observing threat from multiple techniques in breaking secure system. The current trend in breaking the secure system of cryptography is by power analysis technique. In order to break the secure key, the energy consumed in the digital circuit during computation is measured. This technique is commonly known as differential power analysis, explored by the hackers to break the secure systems. To circumvent these type of attacks, it is necessary to explore different designs, which dissipate less energy. Ideally, reversible circuits dissipate zero energy. We present a new reversible architecture for greatest common divisor (GCD) computation using modified Binary GCD algorithm. We present the generalized design methodology of reversible GCD computation unit. We compare the proposed GCD computation design with the existing design. The proposed reversible GCD architecture takes less number of iterations compared with the existing GCD architecture in the literature. The proposed design outperforms the existing GCD design in terms of Quantum Cost, Gate Count, and Ancilla Inputs. Copyright © 2016 John Wiley & Sons, Ltd.