Reverse Engineering for the Purpose of Intellectual Property Protection and Accelerated Product Development in SOC and SIP Structures

Abstract

Technical analysis of intellectual property (IP) is conducted for the purpose of legal protection and product development. A brief review of the process of IP analysis and associated terminology is provided along with examples illustrating the significant potential for monetary benefits to be derived. The evolution of the reverse engineering (RE) process in the semiconductor industry is briefly reviewed from a historical perspective. It is shown how the objective of RE, while continuing its traditional engagement in IP protection, has shifted away from “second sourcing” activities to become an active participant by providing valuable services to technology and product development. The assertion is made that the negative connotation often associated with “reverse engineering” is no longer justified; and the legitimacy, usefulness, and respectability of that process is reaffirmed. The effects of international diffusion of technology are described. It is shown that being aware of technology content in competing high-tech products is now greater than ever before. The process of RE and the “toolbox” of career IP analysts are described through the analysis example of an advanced SOC and SIP structure. The dual utility of the analyst's toolbox and skill set is examined as it is being applied a) to the discovery process aimed at intellectual property protection and b) as a means to accelerate product development. Special attention is given to technical IP analysis conducted in association with new product research and development. Practical examples involving the analysis of advanced 3D structures are provided from the field of 3D integrated product development in order to demonstrate how technical IP analysis can a) help avoid costly mistakes, b) capture design wins, and c) accelerate new product development. The synergistic relationship between IP analysis applied to IP protection and product development is explored; and a coordinated and comprehensive approach to technical IP analysis is recommended whenever practical. A high-tech company will realize maximum benefits from a technical analyst's work if IP analysis of competing products is performed for the purpose of product development with the analyst remaining mindful and attentive of the need to protect corporate patent portfolio. Conversely, knowledge gained from technical analysis aimed at protecting the company's patents can be quite useful to the development engineer. Regardless of whether or not the analyst is an employee of the company or a hired sub-contractor, proper description of the task is crucial from the outset. The analyst should be encouraged to take a dual track approach with primary focus directed towards the main intent (IP protection or engineering analysis of a competing product or technology) without ignoring the secondary purpose. At the end of a project, an assessment should be made as to what part of the acquired knowledge is relevant to the engineering community and what portion of the report needs to be directed to the IP department. Technical IP analysis conducted with this dual purpose in mind is a cost-effective way to maximize return on investment (ROI) in RE. It can also be a powerful tool to reduce the cost of new product development while improving time to market. A new area of technical IP analysis, the extraction of parasitic R, L, C elements from SOC and SIP structures, is explored in detail. This field is believed to be of great importance in 3D integration due to the loss or breakup of ground and power delivery planes as a result of increased reliance on vertical interconnections such as interposers and TSVs. These structures introduce troublesome interconnect inductances, resistances, and capacitances. Both power distribution networks (PDN) and high-speed signal paths are affected by interconnect parasitic elements in component modules such as deep sub-micron 22nm ARM processors, multi-stack memories, and multilayer PCBs of high speed communication devices and systems. It is essential for circuit designers, package designers, and system designers to be aware of these risks as early in the design phase as possible. Practical examples are given how an entire PDN of a larger system including complex 2.5D and 3D packages, substrates, and PCB can be reconstructed from the power source down to individual components, including high-speed data paths. Such reconstruction is done using two-dimensional layer images and via structures. The reconstructed file can be 2D or 3D representation. Depending on the objective, the data residing in those files is then imported into state-of-the art circuit simulation tools familiar to the circuit or package designer. At that point, the circuit, package, or system designer can analyze the entire system and extract all parasitic interconnect elements. The circuit designer can then incorporate all those interconnect and passive component parasitic R, L, C, and M elements or their S-parameter representation into a top-level circuit simulation of an integrated circuit and obtain an accurate circuit performance that is truly representative of the final hardware. In summary, the need for precise modeling of the PDN section and certain high-speed data paths of SOC and SIP structures is reaffirmed, and a case is made for making this sometimes labor intensive process available as part of the technical analysis process. The synergy between reverse engineering conducted for the purpose of IP protection and product development is further emphasized. It is concluded that technical IP analysis, competitor product (hardware) analysis, and product development are activities complementary to one another. These activities, if executed thoughtfully, consistently, and systematically, can not only protect IP, increase intellectual asset value, but can also accelerate product development, guide and fuel innovation, and help in setting the direction of research and development.