Reverse Engineering for 2.5-D Split Manufactured ICs

Abstract

Integrated circuit (IC) split manufacturing has been shown to be one of the most effective protection schemes to prevent reverse engineering from malicious foundries. Among the existing split manufacturing approaches, the 2.5-D split manufacturing using silicon interposer has much less fabrication and testing costs compared to layer splitting approaches. In this article, we propose a Boolean satisfiability (SAT)-based attack to reconstruct the wire connections of the 2.5-D split manufacturing netlists. Our SAT-based attack can fully reconstruct the missing wires between modules with 100% correctness and therefore the functionality of the chip can be completely reverse engineered. In addition, we show that the runtime of attack is significantly reduced compared to existing 2.5-D split manufacturing SAT attacks by applying grouping hints obtained from a satisfiability modulo theories (SMTs)-based grouping algorithm, which is purely depending on the circuit functionality, so no physical defensive mechanisms can prevent such attack. In our experiments, we show that our grouping algorithm can speed up the existing SAT attack runtime by more than $1000\times $ and can successfully reverse engineer reasonable size benchmarks even when the split nets contains more than one fanouts and the total cut size is close to 1000.