Retraction Notice: Method for Ultra-precision FPU Integration based on Fine-Grained Control

Qing-Yu Chen,Long-Sheng Wu

doi:10.2174/1874444301810010041

Abstract

In general, the FPU and processor are decoupled in the method for FPU integration, in which the communica- tion between them requires software intervention and ultra-precision FPU is unsupported. To avoid this problem, a method based on fine-grained control for integration of FPU into the RISC processor is proposed in this paper. In terms of operand width of floating-point instructions, the method divides floating instructions into three categories: S, D and U, and further subdivides the execution status of S, D and U. Then, it regards the execution status as basic granularity to gen- erate the FPU control information and moves the control information needed by destination operands to the next pipeline stage. Finally, segmentation of destination operands is achieved in different pipeline stages and the destination operand is written to register file after segmentation with the pipeline. An 80-bit FPU is embedded into a SPARC V8 processor based on the proposed method. The results of implementation and verification show that the critical path of floating instructions decreases by 37.3%, hardware consumption reduces by 16.9% and the floating-point calculation efficiency increases 1.7 times. The proposed method can be used to apply the ultra-precision FPU embedded into the RISC processor, and to make an efficient collaborative computing between them at low hardware overheads.

Highlights

Various soft computing solutions can be further illustrated based on some particle swarm optimization (PSO) and artificial neural network(ANN) models [1,2,3,4] which are computationally time-consuming or may need parameter estimation [5, 6]
To solve the problem above, a fine-grained integration method for ultra-precision float point unit (FPU), which based on centralized control and data segmentation, is proposed
When the FPU calculation is finished, the various pipeline stages(EX, MA, WB) will register the 80 bits FPU output in segmentation according to the information stored in pipeline registers and WB stage writes the destination operands to floatingpoint register file

Summary

Introduction

Various soft computing solutions can be further illustrated based on some particle swarm optimization (PSO) and artificial neural network(ANN) models [1,2,3,4] which are computationally time-consuming or may need parameter estimation [5, 6]. In addition to model simulation, scientific and real-life applications have more critical requirements for the floating-point performance and data accuracy of embedded processor [7]. The vast majority of processors integrate double precision hardware float point unit (FPU) to improve floating-point performance and data accuracy [8,9,10,11], which can hardly satisfy the actual application. The ultra-precision computing is achieved by software in the contemporary embedded fields [12], which dramatically reduces overall performance of processor [13, 14]. The ultra-precision FPU integration in Reduced Instruction Set Computer (RISC) processor is an important ongoing research of processor design

Methods

Results

Conclusion