Retiming technique for clock period minimization using shortest path algorithm

Abstract

VLSI technology requires three main factors high speed, less power and small chip area. Speed is the factor which always depends upon clock frequency. Computation time of digital circuit can be reduced by applying transformation of delay that is retiming to digital signal block, which can be applied to digital signal processing blocks that can reduce computation time. For transformation of delay we need critical path and shortest path computation algorithm. Clock period minimization techniques of retiming used to minimize clock period of the circuit like Infinite impulse response, Finite impulse respons (IIR, FIR) filters. We have computed critical path before applying retiming in circuit, it gives us an estimation of computing time. Shortest path algorithms are required in the circuit for solving shortest path problem in the graph. We are explaining clock period minimization technique of retiming to enhance speed and proposing new shortest path algorithm. Existing method contain Floyd-Warshall(all pair shortest path) and Bellman Ford algorithms (single point shortest path)which are used in retiming. We are giving new Dijkstra algorithm(single point shortest path algorithm)instead of bellman ford algorithm because it has less run time complexity and high speed. We also observed that most of filter data flow graph are sparse. Then we have chosen Johnson algorithm (all pair shortest path) because run time complexity of it is less than Floyd-Warshall which are existing algorithm. For this purpose used CAD tool for computing run time complexity of overall algorithm.