Retiming and time borrowing

Abstract

Pulsed-latches take advantage of both latches in their high performance and flip-flops in their convenience of timing analysis. To minimize the clock period of pulsed-latch-based circuits for a higher performance, a problem of combined retiming and time borrowing is formulated, where the latter is enabled by using a handful of different pulse widths. The problem is first approached by formulating it as an integer linear programming to lay a theoretical foundation. A heuristic approach is proposed, which solves the problem by performing clock skew scheduling for the minimum clock period and gradually converting skew into a combination of retiming and time borrowing. Experiments with 45-nm technology demonstrate that the clock period close to the minimum can be achieved for all benchmark circuits with an average of 1.03× with less use of extra latches compared to the conventional retiming. Categories and Subject Descriptors: B.6.1 [Logic Design]: Design Styles-Sequential circuits; B.7.1 [Integrated Circuits]: Types and Design Styles-VLSI General Terms: Algorithms, Design