Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p+/i/n+ Silicon Nanowire

Abstract

In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /i/n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> nanowire via well-calibrated TCAD simulations. The 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> at 25 °C and 1-ns read duration) of state “1” to state “0,” and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of ~3 s at 25 °C. The long RT, considering a severe WL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (~3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices.