Result-consistent counter sampling scheme for coarse-fine TDCs

Abstract

A novel sampling scheme for coarse-fine time-to-digital converters (TDCs), whose architecture commonly comprises a synchronous counter as a coarse part and delay-line based phase interpolator as a fine part, is proposed. The presented approach eliminates any error in the coarse counter and is superior in terms of mean time between failures as well as complexity, area and power consumption in comparison to previously reported solutions.